The present invention in general relates to an apparatus with which whether a semiconductor integrated circuit, such as a memory and IP (intellectual property: the functional block of an electronic circuit), is functioning properly, or not, can be determined. More specifically, this invention relates to an apparatus which uses an actual operating frequency for testing the semiconductor integrated circuit.
As an example of the apparatus for testing a semiconductor integrated circuit, an apparatus which is built in the semiconductor integrated circuit (i.e. target for the test or a test target) and which conducts a BIST (Built-In Self Test) is known. The standard specification of a BIST interface is that specified by IEEE1149.1. It is becoming general to actuate the BIST using states and an external dedicated pin prepared in the IEEE1149.1.
FIG. 12 is a block diagram of the conventional semiconductor integrated circuit utilizing the IEEE1149.1. This semiconductor integrated circuit comprises a test target circuit 61. The semiconductor integrated circuit further comprises a test pattern generation circuit 62 which generates a signal to be used for the test (i.e. a test signal) and outputs the test signal to the test target circuit 61, a test result compression circuit 63 which receives a result of the test (i.e. a test result) from the test target circuit 61 and compresses the test result. The semiconductor integrated circuit further comprises a test data register 64 which outputs data to the test pattern generation circuit 62 and receives the compressed test results from the test result compression circuit 63. The semiconductor integrated circuit further comprises a TAPc (test access port controller) 65 which receives a test data-in (TDI) signal and a test mode select (TMS) signal from a not shown signal generation apparatus provided outside the semiconductor integrated circuit, and outputs data to the test data register 64. The semiconductor integrated circuit further comprises a selector circuit 66 which selects either a signal from the test data register 64 or a signal from the TAPc 65 under the control by the TAPc 65 and outputs the selected signal. The semiconductor integrated circuit further comprises a flip-flop (FF) circuit 67 which latches the signal output by the selector circuit 66 at the timing of the falling edge of a test clock (TCK) signal used for the test and outputs the signal to a TDO (test data-out) terminal.
The TAPc 65 outputs a test mode change-over signal (TESTMODE signal) for controlling change-over between a test mode for executing the test and a normal operation mode for conducting a normal operation with respect to the test pattern generation circuit 62 and the test data register 64. While FIG. 12 shows a case where the TAPc 65 sets the TESTMODE signal, the TESTMODE signal may be set directly from the external pin of a chip.
FIG. 13 is a block diagram which shows a detail configuration of the test target circuit 61, the test result compression circuit 63 and the test data register 64 shown in FIG. 12. The test target circuit 61 comprises a plurality of test target blocks 71-1 to 71-3, and test result holding circuits 72-11 to 72-14, 72-21 to 72-23 and 72-31 to 72-33 which receive the test result from the output terminals DO71 to DO74, DO81 to DO83 and DO91 to DO93 of the test target blocks 71-1 to 71-3, respectively, and hold the test results.
The test result compression circuit 63 comprises AND circuits 73-1 to 73-3 which receive the test result shifted out from test result holding circuits 72-1 to 72-14, 72-21 to 72-23 and 72-31 to 72-33 corresponding to the respective test blocks 71-1 to 71-3 at input terminals thereof, and holding circuits 74-1 to 74-3 holding the output signals of the respective AND circuits 73-1 to 73-3 and outputting the held signals to the other input terminals of the respective AND circuits 73-1 to 73-3 and to the test data register 64.
The test target circuit 61, the test pattern generation circuit 62 and the test result compression circuit 63 operate using a system clock (SYSCLK) signal with an actual operating frequency. On the other hand, the test data register 64 and the TAPc 65 operate using a TCK signal with a lower frequency than the actual operating frequency. The test result compression circuit 63 compresses the test results from the output terminals DO71 to DO74, DO81 to DO83 and DO91 to DO93 into one bit for the test target blocks 71-1 to 71-3, respectively, and outputs the compressed test results to the test data register 64. The number n of bits of the test data register 64 is set higher than the number m of bits after compression by the test result compression circuit 63.
Operation of this semiconductor integrated circuit will now be explained. To begin with, an instruction to select the test data register 64 is applied to the IR (instruction register) of the TAPc 65. When such an instruction is received, the TESTMODE signal changes from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d and the semiconductor integrated circuit shifts into a test mode. Next, the instruction is set to the test data register 64 in a ShiftDR state. The instruction is applied from the test data register 64 to the test pattern generation circuit 62 in an UpdateDR state. A BIST is then executed in a RunTest/Idle state and a test result is acquired. This test result is compressed by the test result compression circuit 63. In a CaptureDR state, the test results compressed by the test result compression circuit 63 are stored in the test data register 64. In a ShiftDR state, the data stored in the test data register 64 is outputted from the TDO terminal.
As can be seen, initial settings and test results are outputted to the TDO terminal using the low frequency TCK signal. The test operation is carried out using the SYSCLK signal with an actual operating frequency which is used when the semiconductor integrated circuit actually operates. By doing so, it is possible to decelerate signals, other than the SYSCLK signal, and to reduce tester cost.
The conventional technique has the following disadvantages. That is, a faulty section cannot be pinpointed accurately since the test results are outputted after being compressed. Such a detailed faulty section can be specified if a test data register with the same number of bits as that of the bits of the test result holding circuits is provided and test results are outputted without being compressed. However, this results in an increase of the size of the test data register and increase of the number of wires between the test result holding circuits and the test data register and it is, therefore, not practical.
It is an object of the present invention to provide an apparatus accurately pinpointing a faulty section in a semiconductor integrated circuit without increasing the scale of the apparatus.
The apparatus according to the present invention uses the actual operating frequency when testing the semiconductor integrated circuit. The apparatus comprises a test circuit having a scan path formed for executing a test and a control circuit which generates, after completion of the test, a scan-out control signal for scanning out a test result synchronously with an edge of a test clock signal with a lower frequency than the actual operating frequency, and outputs the scan-out control signal to the test circuit. Thus, the test circuit having the scan path tests the semiconductor integrated circuit, and, after the completion of the test, the control circuit generates a scan-out control signal for scanning out a test result synchronously with the edge of a test clock signal with a lower frequency than the actual operating frequency and outputs the scan-out control signal to the test circuit. By doing so, it is possible to output an uncompressed test result at the timing of the test clock signal.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.